cpu usage - CPU memory access time -

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does average data , instruction access time of cpu depends on execution time of instruction? example if miss ratio 0.1, 50% instructions need memory access,l1 access time 3 clock cycles, mis penalty 20 , instructions execute in 1 cycles average memory access time?

i'm assume you're talking cisc architecture compute instructions can have memory references. if have sequence of adds access memory, memory requests come more sequence of same number of divs, because divs take longer. won't affect time of memory access -- locality of reference affect average memory access time.

if you're talking risc arch, have separate memory access instructions. if memory instructions have miss rate of 10%, average access latency l1 access time (3 cycles hit or miss) plus l1 miss penalty times miss rate (0.1 * 20), totaling average access time of 5 cycles.

if half of instructions memory instructions, factor clocks per instruction (cpi), depend on miss rate , dependency stalls. cpi affected extent memory access time can overlap computation, case in out-of-order processor.

i can't answer question lot better because you're not being specific. in computer architecture class, have learn how figure out how compute average access times , cpi.


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