c - GAUT HLS tool error : "No alternatives to process, unable to select best one" -

i trying synthetise following c code using gaut tool:

#define n 16   int main (const int tab[n], int* out) {  //  static const int tab[n] =        {98,-39,-327,439,950,-2097,-1674,9883,9883,-1674,-2097,950,439,-327,-39,98};     int k = 0, i=1;    for( = 1; < n; i++) {           // invariant : k est l'indice du plus petit       // élément de x[0..i-1]       if(tab[i] < tab[k])           k = i; }    *out = tab[k];   return 0;       } 

simple program find minimum in array. compiles, generates dfg seems honest. when try synthetise, error: "no alternatives process, unable select best one" , can't go on implementation flow.

does know problem? facing other such small test programs well. hope specialist able answer.

thank you.

since tagged vhdl, perhaps it's worth looking @ straight vhdl port, bypassing tool completely. took few minutes, , it's in 3 parts:

1) vhdl has quirk in use array port parameter, must named type (int_array). (c has different quirk passing arrays around : doesn't, passes pointer instead)

package types type int_array array (natural range <>) of integer; end types;  package body types end types; 

2) bit work: left c code in comment illustrate how closely correspond:

use work.types.all;  -- int main (const int tab[n], int* out) entity minarray    generic ( n : natural);    port ( tab : in int_array;            output : out integer ); end minarray;  architecture behavioral of minarray --  int k = 0, i=1; -- for( = 1; < n; i++) --   {    --      if(tab[i] < tab[k]) --          k = i; --   } --  *out = tab[k]; --  return 0;      --} begin    process(tab)     variable k : natural;     begin        k := 1;        in tab'range loop            if tab(i) < tab(k)                k := i;           end if;         end loop;        output <= tab(k);     end process; end behavioral; 

3) test harness:

  use work.types.all;    entity tester      port ( minimum : out integer );   end tester;    architecture behavior of tester   --#define n 16 -- static const int tab[n] =        {98,-39,-327,439,950,-2097,-1674,9883,9883,-1674,-2097,950,439,-327,-39,98};    constant n : natural := 16;   constant tab : int_array (1 n)  := (98,-39,-327,439,950,-2097,-1674,9883,9883,-1674,-2097,950,439,-327,-39,98 );    begin           uut: entity work.minarray                  generic map (n => n)                 port map(                 tab => tab,                  output => minimum );    end; 

note synthesisable in xilinx xst,

advanced hdl synthesis report  macro statistics # rams                                                 : 1  32x32-bit single-port distributed read ram       : 1 # comparators                                          : 15  32-bit comparator greater                             : 15 # multiplexers                                         : 32  1-bit 2-to-1 multiplexer                              : 24  2-bit 2-to-1 multiplexer                              : 1  3-bit 2-to-1 multiplexer                              : 4  4-bit 2-to-1 multiplexer                              : 3 

but (because input tables constant array) above hardware disappears in optimisation stage.

now 1 of important things in high level synthesis explore different datatypes such different word widths; such 15-bit word required store test data. explore this, let's modify "types" package follows:

type small_int range -16384 16383; type int_array array (natural range <>) of small_int; 

i changed output port type small_int. , can see synthesis report, hardware usage has been reduced accordingly.

macro statistics # rams                                                 : 1  32x15-bit single-port distributed read ram       : 1 # comparators                                          : 15  15-bit comparator greater                             : 15 # multiplexers                                         : 32  1-bit 2-to-1 multiplexer                              : 24  2-bit 2-to-1 multiplexer                              : 1  3-bit 2-to-1 multiplexer                              : 4  4-bit 2-to-1 multiplexer                              : 3 

so perhaps question : how easier c tools make exploring design space custom word widths?